Memory modules, referred to in the following text as DIMM (dual in-line memory modules) have a defined physical extent. Owing to the finite propagation speed of electrical signals, the physical extent of the DIMM thus corresponds to a delay time for the electrical signal for passing from a signal source to a signal sink. This phenomenon is generally referred to as the “line effect”, which means that the “electrical length” of the interconnects can no longer be ignored. This is the situation when the highest frequency component which occurs in the signal is at a wavelength which is in the same order of magnitude as the physical extent between the signal source and the signal sink.
The higher the data rate on a DIMM, the higher are the frequencies of these frequency components and the shorter are the physical extents for which this line effect must be taken into account. Present-day memory developments are using data rates DR which, as a result of the described subject, are leading to major time-critical problems. These present memory module developments have the particular characteristic feature of a central integrated circuit (IC) or memory buffer which is mounted on each DIMM. This IC produces the electrical signals for communication with the memory modules locally, that is to say on the DIMM.
This basic design according to the state of the art is shown in FIG. 1. As can be seen, a range of different signals are indicated here, which are either of different length (DQ/DQS) or else are received simultaneously by a large number of memory modules (CA).
The HUB in the center of the dual in-line memory module (DIMM) is connected via bi-directional data transmission lines forming a data bus to the DRAM chips on the same memory module. Further the HUB or memory buffer is connected via a command and address bus (CA) to the DRAMs. The dual in-line memory module as shown in Figure in FIG. 1 can be connected to a motherboard comprising a microprocessor. The HUB or memory buffer in the center of the dual in-line memory module is connected via a data bus to the microprocessor and provides the microprocessor with data read from the DRAMs. Since distances of the DRAMs to the memory buffer are different data read from the DRAMs will reach the HUB or memory buffer in the center of the dual in-line memory module at different times due to the signal propagation time.
FIG. 2 shows a block diagram of a dual in-line memory module having a command and address bus and data buses connecting each DRAM to the central HUB.
FIG. 3 shows a general arrangement, according to the state of the art which comprises a central receiver (HUB) and X transmitting DRAM-modules. The overall data bus has a width of n bits, so that each transmitting DRAM-transmits a data bus component of n/N bits. By way of example, a 72 bit data bus of a DIMM comprising DRAMs can in each case be implemented with an 8 bit data bus component. The described line effects mean that data is subject to different delay times on different interconnects. At the time t1, all n transmitting DRAMs simultaneously send their data bus component to the receiver provided within said memory buffer (HUB). Owing to the different delay times, which are caused by the different distances between the transmitting DRAMs and the receiver within the HUB, the individual data bus components reach the receiver at different times (times t2, t3 and t4). However, for parallel data transmission it is necessary that all the information units (bits) which belong to one entire data word must reach the receiver within one transmission clock cycle. In a conventional arrangement this fact leads to a limitation to the maximum data transmission rate on the data bus, since the faster data signals originating from the DRAMs close to the HUB have always to wait for the slower signals of the more distant DRAMs before a new transmission cycle can be started.
FIG. 4 illustrates the problem that the integrity of the data signals transmitted on a parallel data bus is threatened by the different line delay times. As can be seen from FIG. 4, the receiver cannot accept the data until, at the earliest, the “data complete” time. This also shows that the maximum data rate DR max is influenced by this. The transmitter which is closest to the receiver (HUB) must not start to transmit the next data item until all the other (slower) data items have reached the receiver.
A conventional method according to the sate of the art for compensating for different delay times is for the interconnects to be routed in a meandering shape on the printed circuit board (PCB). However, this conventional compensating method is quite unsuitable for many applications because the meanders require additional space on the printed circuit board.
Another method according to the state of the art defines an additional reference channel with a defined data content between the transmitter an receiver. However, since there are a number of receiver modules on one DIMM, this additionally increases the complexity. These known prior art methods are therefore suitable only to a limited extent for determining and compensating for the delay time of data bits.